1. Field of the Invention
The present invention relates to a method for fabricating an insulating gate field effect transistor such as an MOS transistor suppressing the so-called short channel effect.
2. Description of the Related Art
As one of means for improving the performance of an MOS transistor, it is well known to make the channel length thereof short. In accordance with shortening in channel length, however, the electric field applied near the drain region of the transistor becomes stronger because of an abrupt impurity profile thereof. In order to reduce the electric field, therefor, such an MOS transistor that has a lightly doped drain (LDD) structure have been proposed and put into practical use.
Referring to FIGS. 3(a) to 3(c), such an LDD transistor is fabricated as follows:
First, a field oxide film 202 and a gate oxide film 203 are formed by the thermal oxidation of an element isolation region and an element formation region, respectively, of a P-type silicon substrate 201 having an impurity concentration of about 10.sup.15 cm.sup.-3. After implantation of boron ions for threshold voltage adjustment under conditions of, for example, 35 keV and 4.times.10.sup.12 cm.sup.-2, a 300 nm-thick polycrystalline silicon film is formed over the entire surface by the chemical vapor deposition (CVD) method and then diffused with phosphorus impurities, followed by patterning to form a gate electrode 204. Phosphorus ions are implanted at, for example, 20 keV and 7.times.10.sup.13 cm.sup.-2 in a self-alignment manner with the gate electrode 204 and the field oxide film 202 to form N.sup.- -type lightly-doped layers 205a and 205b having an impurity concentration of about 10.sup.18 cm.sup.-3. A silicon oxide film 206 with thickness of about 150 nm is then formed allover the surface by the CVD method (FIG. 3(a)).
Next, as shown in FIG. 3(b), the silicon oxide film 206 is etched back by the anisotropic reactive ion etching (RIE) method to leave and thus form silicon sidewall spacers 206a on the both side of the gate electrode 204. Arsenic ions are implanted at, for example, 70 keV and 3.times.10.sup.15 cm.sup.-2 in a self-alignment manner with the silicon oxide spacers 206a, the gate electrode 204 and the field oxide film 202 to thereby form highly-doped N.sup.+ -type diffused layers 207a and 207b having an impurity concentration of about 1.times.10.sup.19 cm.sup.-3 In this way, a source region 208 consisting of the N.sup.- -type diffused layer 205a and the N.sup.- -type diffused layer 207a, and a drain region 209 consisting of the N.sup.- -type diffused layer 205b and the N.sup.- -type diffused layer 207b, are formed.
Following that, as shown in FIG. 3(c), a silicon oxide film 210 with thickness of about 100 nm is formed on the entire surface by the CVD method. Then, a BPSG film with thickness of about 700 nm is formed on the entire surface by a atmospheric pressure chemical vapor deposition (APCVD) which uses tetraethoxysilane (Si(OC.sub.2 H.sub.5).sub.4 ; TEOS) gas, ozone (O.sub.3) gas, trimethylphosphate (PO(OCH.sub.3).sub.3 ; TMP) gas, and trimethylborate (B(OCH.sub.3).sub.3 ; TMB) gas as source gases and further a spin-on-glass (SOG) film (not shown) is formed on the entire surface. The silicon oxide film is etched back until the SOG film is removed completely to thereby form a BPSG film 211 having a flat top surface. Contact openings which reach respectively the source region 208 and the drain region 209 are formed by RIE by sequential etching of the BPSG film 211 and the silicon oxide film 210. A titanium film 212 with thickness of about 60 nm and a titanium nitride film 213 with thickness of about 100 nm are formed on the entire surface by sputtering and reactive sputtering, respectively. Further, the surface is blanketed with a tungsten film having a thickness of about 500 nm, and the tungsten film is etched back leaving a tungsten film 214 within the contact openings. Then, an aluminum film 215 with thickness of, for example, about 500 nm is formed by sputtering and then patterned to form metallic wirings each composed of the aluminum film 215, the titanium nitride film 213 and the titanium film 212. Next, an inter-layer insulating film 216 is formed on the entire surface. Thus, the LDD MOS transistor is derived.
Although the LDD MOS transistor presents an improved performance, in order to further enhance the device performance, the reduction in the parasitic or stray capacity of the MOS transistor itself becomes also important. The MOS transistor inherently has the stray capacitances between the gate and channel and between the gate and source/drain. In the LDD structure, however, each of the gate length (L) and the gate width (W) is reduced and further the lightly-doped regions 205 is suppressed to extend laterally. Therefore, the overlap capacitance between the gate electrode and the channel region is decreased.
However, the decrease in the overlap capacitance causes in turn the rate of the so-called fringe capacitance to increase. The fringe capacitance is formed between the gate electrode and the source/drain region due to the fringe electric fields between the sides of the gate electrode and the source/drain region. That is, the fringe capacitance becomes in turn one of major factors influencing the operating speed of the transistor.
For example, in the transistor shown in FIG. 3, the fringe capacity between the gate electrode and the drain region is about 1.24 fF, for L=0.5 .mu.m and W=10 .mu.m. When this transistor is employed to constitute a CMOS inverter together with a P-channel transistor with L=0.5 .mu.m and W=15 .mu.m, the delay time of the inverter becomes the order of 100 ps.
In order to reduce the fringe capacitance, therefore, it may be considered that the inter-layer insulating film 211 is replaced with a polyimide film having a low dielectric constant. In this case, however, the polyimide layer generates an organic gas upon sputting the metal film 212, so that many voids in the metal layer.
It may be further considered that the silicon oxide side spacer 206 is replaced with a low dielectric film such as polyimide. In that case, a polyimide film is deposited over the entire surface in place of the oxide film 206 and then etched back to form a polyimide side spacer, followed by forming the regions 207a and 207b. However, the polyimide space hardly operates as a mask for selective ion-implantation, so that undesirably large highly-doped regions are formed. Moreover, it is not easy to control the width of the polyimide spacer.